1. Field of the Invention
The present invention relates to an image processing method and apparatus for inputting an image signal, processing the inputted image signal and outputting the result.
2. Descriptions of the Related Art
In an image processing apparatus, an original image is read by an image sensor such as a CCD and an obtained luminance signal is logarithmically transformed to generate a density signal proportional to a recorded density. Herein, since the luminance signal obtained from the sensor is a raster signal of every line, a LUT (look-up table) conversion is performed utilizing a memory of 256 words having eight address terminals, for a logarithmic transformation of an image signal with one pixel having 8 bits. A non-linear data conversion of this type is not limited to a logarithmic transformation, and other various conversions such as a .gamma.-conversion for density adjustment, a conversion for correcting recording unevenness of solid recording elements or the like are known.
Further, an edge emphasizing process or a smoothing process are performed on the image signal. Still further, a calculation such as multiplying of the image data by matrix data representative of a two-dimensional space filter is performed for a pattern recognition process or the like for recognizing the image. The calculation is complicated and must be executed every time one pixel is read; therefore, it is necessary to two-dimensionally store all the read image signals in a predetermined area and execute multiplication and summing on the stored two-dimensional image signals.
Recently, a DSP (digital signal processor), developed for the purpose of an image processing, which comprises a number of arithmetic logic units (ALUs) for a real-time process of high-speed video signals such as an NTSC signal, makes it possible to process pixel data of one raster in parallel at each processor.
Generally, the above described image processing is performed utilizing a look-up table (LUT). Such image processing where image data is converted by the LUT has an advantage that the process can be serially executed with a single LUT without considering the number of pixels in one raster. However, in order to perform this type of image processing utilizing the above described DSP which enables parallel processing, a memory for the LUT is necessary having as many storage locations as the numbers of bits compressing the pixels; therefore, the size of the LUT becomes extremely large, thereby making it difficult to realize.
Taking a DSP (SVP: scan-line video processor) made by Texas Instrument, Inc. as an example, the bit numbers of each register simultaneously-usable for calculating each pixel data is 256 bit. Therefore, if the foregoing LUT conversion is to be performed, the capacity of a register must be ten times larger than the one currently used.
Further in the above-described multiplication and summing calculation, if an image processing area for the image data is extended, the circuit structure becomes large and expensive; therefore, an inexpensive circuit structure cannot be achieved. Even if a circuit utilizing the above described DSP is utilized, the image data area subjected to be processed is limited by the DSP specification. Further, even if an image processing in a wide area is possible, the processing by the DSP cannot be completed within a predetermined time.